Package-On-Package Interconnect For Fan-Out Wafer Level PackagesAuthors: Min Tao, Ph.D, Akash Agrawal, Ashok Prabhu, Ilyas Mohammed, Ph.D, Belgacem Haba, Ph.D
Company: Invensas Corporation
Date Published: 10/18/2016 Conference: IWLPC (Wafer-Level Packaging)
The FOWLP POP technologies available in the market fall into two main process categories: chip first, such as TSMC’s integrated Fan-Out (InFO) POP  and Stats Chip Pac’s encapsulated Wafer Level BGA (eWLB) ; and chip last, such as Amkor’s Silicon-Less Integrated Module (SLIM) and Silicon Wafer Integrated Fan-Out Technology (SWIFT) . The compatibility of POP interconnect selection with the process flow, POP interconnect pitch capability, stack thickness, and potential issues of each approach will be discussed.
BVA as an POP interconnect option in FOWLP can be incorporated into either a chip first or a chip last approach. In this paper, the materials and process details describing BVA bonding onto a conventional Redistribution Layer (RDL) build up structure are discussed and the bonding feasibility is demonstrated.
Fan-out Wafer Level Package, Package-On-Package Interconnect, Bonded Via Array
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