IWLPC (Wafer-Level Packaging) Conference Proceedings


Silicon Wafer Integrated Fan-Out Technology

Authors: Bora Baloglu, Ph.D., George Scott, and Curtis Zwenger
Company: Amkor Technology, Inc.
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The continued scaling of transistor geometries for semiconductor devices has been placing an increased demand on the next-level interconnect technologies. Heterogeneous integration of memory and logic devices is increasingly becoming the norm for next generation mobile, high performance graphics, and network applications. This requires advanced packaging technologies with capabilities for very high signal routing densities, efficient power distribution, and superior signal integrity. In addition, 3D package integration is often required, especially for mobile applications. This places an increased emphasis on the package technology’s z-height reduction and thermal performance capabilities.

Traditional organic laminate substrates that apply flip chip bonding have met the semiconductor industry’s advanced interconnection needs for over 15 years [1]. With the continued advancements in materials and processes, laminate substrates are expected to satisfy the majority of advanced package performance and cost requirements for years to come. However, the feature size limitations and the electrical and thermal performance constraints will continue to restrict laminate substrates from meeting the integration requirements for next generation mobile, high performance graphics, and networking applications.

Emerging silicon-based interconnection technologies, such as through silicon via (TSV) have shown promise in this area. By leveraging the back end of line (BEOL) damascene processes of the wafer fab, multi-layer sub-micron signal trace densities can be achieved. However, the supply chain limitations and intrinsic cost implications have limited the proliferation of 3D IC technology. In particular, for silicon interposers, there can be an undesirable effect to z-height and electrical performance due to the inherent thickness and parasitics of the silicon interposer.

This paper introduces an innovative high density fan-out (HD-FO) semiconductor packaging technology that bridges the gap between organic laminate-based substrates and inorganic foundry-based silicon interconnection technologies. Silicon Wafer Integrated Fan-out Technology (SWIFT™), also called chip last HD-FO, incorporates the fine feature size capabilities of wafer-level packaging (WLP) coupled with the advanced flip chip packaging technologies, such as chip on wafer (CoW) and Package-on-Package (PoP). The result is a highly integrated structure that has exceptional electrical, mechanical, and thermal performance benefits – compared to incumbent packaging technologies – to meet the needs of next generation mobile, high performance graphics, and network applications.

Key Words: 

SWIFT™, 3D, PoP, Fan Out, WLFO, HD-FO, Chip Last



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