IWLPC (Wafer-Level Packaging) Conference Proceedings

Wafer Level System in Packaging (SIP) Technologies As 2, 3D Module/ System Integration Solution

Authors: Jong Heon KIM, Yong Tae KWON, Eung Joo LEE, JK Lee, Seo Hee LEE
Company: nepes Corporation
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Recently, fast growing market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications are driving FOWLP technology to miniaturize 2D & 3D integration. Fan Out Wafer Level Packaging (FOWLP) has been introduced as a solution to overcome the limitation of conventional wafer level package as well as cost-performance-form factor alternative solution of flip chip package and wire bonding package. Furthermore, fan-out technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has introduced several advanced package platforms (Single, multi dies and 2D, 3D) through FOWLP and embedding technologies. nepes’ SiP solution of FOWLP offers 40~90 % of volumetric shrink from existing module with flexibility of product design for end user. Numerous active or passive components are embedded and connected in 2D and 3D with via connection to backside of package for PoP (Package on Package) structure which is designed for communication module and system control application. 3D module using two kinds of FOWLP (Fan-Out Wafer Level Package) as PoP structure with JEDEC MSL Level 2 for reliability evaluation has been developed.

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