SMTA International Conference Proceedings


CHIP SCALE PACKAGE SOLDER PASTE STENCIL PRINTING OPTIMIZATION

Author: Tom Long
Company: ITT Aerospace/Communications
Date Published: 9/12/1999   Conference: SMTA International


Abstract: Chip Scale Packages are small components roughly 1 to 1.2 times the size of bare die and use approximately 25% of the area that current Quad Flat Packs use today as shown in figure 1. This advanced packaging component has .012” diameter attachment sites as shown in figure 2. The challenge to assemblers is to determine which parameters in the screen printing process will yield consistent solder paste deposition for these small apertures over varying stencil thicknesses. As we move towards smaller, denser assemblies in a high reliability environment, the ability to consistently print a desired thickness of solder paste has become increasingly critical. As mentioned in IPC D-279 section 3.5.1.3: “The solder joint height determines the strain level experienced in the solder joint for a given component/substrate displacement. Higher solder columns reduce the strains in the solder joints and increase reliability.”

A dynamic Taguchi S/N L18 experiment was performed which analyzed the level effects of seven (7) control factors and two (2) noise factors over a three level signal factor. The results of this experiment have optimized the screen printing process and demonstrated consistent solder deposition thickness across all target configurations. The results of this Taguchi optimization will be used in an assembly optimization later this year examining solder joint reliability for Chip Scale Packages.



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