Symposium Conference Proceedings

Large Panel Wafer Level Packaging

Author: John Almiranez
Company: Universal Instruments Corporation
Date Published: 4/12/2016   Conference: Symposium

Abstract: The world of mobile gadgetry continues to evolve at a rapid pace. For many aspects, people can’t decide what they want: bigger, or smaller? Implantable, wearable or just plain mobile? One aspect is certain: we like thin, light, multifunction, high performance devices. For these products, the electronics inside must be sophisticated enough to support multiple functions, the memory must be sufficiently large yet compact, and power storage is needed to support an acceptable length of usage. All these features have to be packaged in a relatively small form factor.

These thin form factors, combined with high performance, make wafer level packaging an essential technology. Not long time ago, mobile devices consisted of BGAs, CSPs, SOICs, chip passive components and other discrete components. Usually, they were assembled side-by-side in one flat patterned PCB substrate.

Wafer level packaging is driven by the need for thin dies, thin and flexible substrates and tiny passive components. The manufacturing challenges created by this packaging include how material is processed and assembled. Assembly equipment is being forced to adapt to support this. New techniques and careful handling of substrate are required. Effective and efficient die attach methods must be considered. Combining passives and multiple dies is becoming necessary. Stacking dies or so called 3D or 2.5D die attach assembly is being presented in different fashion. All these things must be done in the most productive way, such that a packaging house and production floor can achieve business profitability.

In this paper, one of these challenges shall be addressed by providing a packaging technique focusing on die attach on the largest panel.

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