Surface Mount International Conference Proceedings


CSP DESIGN AND MICROVIA PWB FABRICATION (PART A OF CSP CONSORTIA ACTMTIES: PROGRAM OBJECTIVES AND STATUS)

Author: E.J. Simeus
Company: Raytheon Systems Company
Date Published: 8/23/1998   Conference: Surface Mount International


Abstract: Chip scale packaging technology (CSP) has received much attention over the past two years due to its small size and packaging architecture. Many high volume commercial, aerospace, and defense companies are quickly realizing the benefits of using this technology for packaging memory devices. Since the beginning of 1997, Raytheon Systems Company has been actively involved with a CSP consortium composed of many diverse companies tasked to assess the overall infrastructure of chip scale packaging including design, manufacturing assembly, and reliability. As part of the consortium agreement, Raytheon is responsible for the design and the microvia Printed wiring board (PWB) fabrication of the test vehicle to be used for reliability studies. As packaging densities continue to increase, the design criteria become increasingly critical. Because of the many chip scale package design configurations existing on the market, it is necessary to develop standard guidelines in the design and fabrication of the PWB using CSPs. The focus of this paper is to present lessons learned and issues associated with CSP design and microvia PWB fabrication and possible solutions to these problems. Keywords: CSP, BGA, Consortium, In-kind, PWB, Microvia, Daisy Chain



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