Thermo-Mechanical Warpage and Stress Simulation for 2.5D and 3D IC Packaging
Authors: Akash Agrawal, Guilian Gao, Bongsub Lee, Laura Mirkarimi, Sitaram Arkalgud Company: Invensas Corporation Date Published: 9/27/2015
Abstract: 2.5D and 3D IC fabrication and packaging has many unique challenges that impact final yield. Among them are thin wafer handling and package warpage control. In addition to the stress and warpage generated due to the difference in coefficient of thermal expansion (CTE) between various materials in the package, critical fabrication and assembly processes such as wafer thinning, Chemical-Mechanical Polishing (CMP), chip stacking, cavity filling etc. also impact on assembly yield, performance and reliability of the final product. Before choosing a particular fabrication and assembly flow, it is important to understand how each step affects the thin wafer and final package warpage. The interposer itself may contain severe warpage due to its unbalanced structure and residual stresses from layer deposition processes. In this paper, we discuss a new concept of cavity handle wafer and the effect of wafer level processing on the stress and warpage. A detailed quarter symmetry finite element model of a Chip to Wafer (C2W) 3D stack assembly was built, and multiple thermomechanical step by step simulations were performed to capture the substrate warpage at each assembly step. Interposer warpage and stress were simulated to demonstrate the effect of different cavity handle wafer designs. Also, a parametric simulation study was conducted to optimize the design and materials of 3D stack assembly. With specific materials and optimized design, the warpage of C2W 3D stack interposer assembly used in this study can be reduced to less than 50um.
2.5D, 3D IC, interposer, CTE, warpage, chip stacking, finite element simulation