Solder Joint Fatigue Characterization of DDR3 SDRAMS and Other Advanced BGA Packaging Memory Types
Authors: Arnaud Grivon, Damien Baudet, Michel Brizoux, Aurélien Lecavelier, and Wilson Maia Company: Thales Global Services Date Published: 9/27/2015
Abstract: DDR3 SDRAMs and other kinds of memories consist of compact electronic devices that feature a high memory density, minimized power consumption and high-speed operation. These enhanced components are typically housed in small form factor rectangle BGAs including leading-edge chips as well as advanced packaging technologies. Memory dies are typically produced with the latest IC semiconductor lithography technologies mostly with process nodes below 50nm. Also, dies are frequently thinned and stacked to maximize the overall memory density. Overall, memory devices use dense BGA packages with elevated silicon-toplastic ratios that induce a high board-level reliability risk. To characterize the solder joint fatigue of such devices, an extensive reliability test program has been set-up and conducted on a variety of lead-free BGA memories from different vendors, focusing on DDR3 SDRAMs. This program relied on daisy-chain components mounted on dedicated multilayer test vehicle PCBs that were submitted to an accelerated thermal cycling test in the -55°C/+125°C range during 3000 cycles. A continuous electrical monitoring of the daisy-chained devices was used to record the time-to-failure and determine the solder joint fatigue life during the thermal cycling test. In addition, mirrored configurations were introduced in the PCB test vehicle design to analyze the effect of this configuration on reliability. Finally, some mirrored BGA memory devices were underfilled with a high-Tg epoxy resin with the objective to evaluate the reliability enhancement that could be offered by this ruggedization process.