SMTA International Conference Proceedings


Assembly Challenges for 2.5D and 3D IC Packaging

Authors: Charles G. Woychik, Guilian Gao, Cyprian Uzoh, Hong Shen, Liang Wang, Sangil Lee, Roseann Alatorre, Scott McGrath, Mohamed Elassar and Sitaram Arkalgud
Company: Invensas Corporation
Date Published: 9/27/2015   Conference: SMTA International


Abstract: Stacked packages utilizing through silicon vias (TSVs) are gaining momentum in the industry. While offering considerable performance advantages, the industry is still pursuing multiple integration options. In this work, we explored assembly centric and fab centric reference flows, with a focus on the type of interconnections used for the assembly of micro-bumped die to a Si-interposer. The first type of interconnection was a solder capped Cu-pillar and the second type was a Cu to Cu thermal compression bond. Two different test vehicles were designed and evaluated using each type of interconnection. The process and the assembly challenges encountered during the fabrication and assembly of the test vehicles will be presented here. In the first test vehicle, two 10mm x 12 mm micro-bumped die (MBD) having solder capped Cupillars with a 60um pitch were attached to a 19mm x 27mm Si-interposer with a thickness of 100um and TSVs dimension of 10um x 100um. This Si-assembly was then attached to a buildup substrate. In the second test vehicle, four 9mm square die having 30um pitch Cu pads were attached to a 50um thick Si-interposer containing TSVs with a dimension of 5um x 50um, using Cu direct bonding. This Si-assembly was then attached to a buildup substrate. A discussion of the challenges for both types of assembly approaches will be presented along with detailed characterization of assembly flows.

Key Words: 

2.5D, 3D IC, TSV, Micro-bumped die, Siinterposer, CTE, warpage, JEDEC reliability specifications, chip stacking



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