Symposium Conference Proceedings

TSV Barriers Create SMT Opportunities

Authors: Charles E. Bauer, Ph.D. and Herbert J. Neuhaus, Ph.D.
Company: TechLead Corporation
Date Published: 4/8/2014   Conference: Symposium

Abstract: TSV stands out as a 3D device integration approach (as opposed to 3D packaging method) and promises unrivaled system performance improvements due to short, low impedance interconnect and high silicon efficiency derived from a 3D architecture without the need for a 3D semiconductor fabrication technology. On the other hand, no other 3D approach disrupts the existing supply chain so dramatically. TSV requires a complete restructuring of design, fabrication, and assembly and has yet to offer a solution to the yield challenges associated with known good die (KGD) and wafer/die level assembly processes.

TSV alternatives such as Package-on-Package (PoP), offer real, albeit less dramatic, system performance improvements with far less supply chain disruption. While more difficult than conventional SMT, high yield, cost-effective PoP processes perform well today both in terms of benefits and manufacturability, enabling SMT organizations to capture market share while TSV R&D consumes resources.

This paper analyzes SMT opportunities created by PoP vs TSV in terms of time-to-market, infrastructure compatibility and capital equipment utilization, throughput, design flexibility, and yield. The authors show that, while TSV continues to hold great promise, PoP represents an attractive strategy for SMT facilities wishing to increase profitability and expand into new markets.

Key Words: 

Though Silicon Via, TSV Package-on-Package, PoP, 3D packaging

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