Symposium Conference Proceedings


Cool Substrate for 2.5D Packages

Authors: Charles Lin, Ph.D., Nick Wang, Jerry Tan
Company: Bridge Semiconductor Corporation
Date Published: 4/14/2015   Conference: Symposium


Abstract: Recent demands in system integration and high data transmission are challenging single chip and multi-chip packaging technologies with extremely tight pad pitch and large die size. As high I/O and fine pitch devices are increasingly being introduced, there is a critical need for a packaging substrate having ultra-fine line routing capability in order to deliver the desired performances with better power and signal integrity. Other features such as low CTE and low warpage are also essential to a packaging substrate as the bump height tolerance of a high I/O, large die size devices are extremely tight.

This paper will describe a scalable 2.5D solution using a substrate having interposer or chip carrier integrated therein. Not only conventional silicon interposer, other types of chip carrier such as organic, glass, and ceramic interposer can also be integrated with the organic laminate depending on cost and routing density requirements. The organic laminate in this integrated substrate is a buildup layers without a core. By using a smart combination of interposer and buildup layers manufacturing processes, this integrated substrate allows a very high pin-count and high performance flip chip assembly without incurring any expensive new equipment and new tooling. The integrated substrate, namely, Carrieron- Organic-Laminate (COOL) can support other benefits such as allowing package-on-package assembly will be addressed as well.

Key Words: 

flip chip packaging, coreless substrate, interposer, 2.5D, 3D, FO-WLP (fan-out wafer level packaging), POP (package-on-package), embedded die



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