IWLPC (Wafer-Level Packaging) Conference Proceedings


Unique Polymer Coating Process for Improving Performance and Reliability of 3D Wafer Level Packaging

Authors: Antun Peic, Ph.D., Felix Massa, Johanna Bartel, Thorsten Matthias, Ph.D., Markus Wimplinger, Thomas Uhrmann, Ph.D., and Paul Lindner
Company: EV Group
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: A novel polymer coating technique has been developed for alleviating thermal stress issues intrinsic to copperfilled through silicon via (TSV) interconnect structures. This scalable generic process applies photoresist and optionally also other functional polymer linings at and within TSV geometries to act as a stress buffer at the silicon/copper interface.

Utilizing EVG®NanoSprayTM technology, this technique can create passivation layers that protect against corrosion, but also provide isolation to reduce electrical substrate noise, as well as create compliant layers to mitigate thermo-mechanical stress. [1,2] Investigations on polymer-lined TSVs have demonstrated electrical improvements, including a significant reduction in capacitance density compared to conventional SiO2 insulating TSVs as well as an outstanding reduction in leakage current. [1,2] Herein we present an investigation based on finite element analysis (FEA) results for different TSV types with polymer-coated via sidewalls. In particular, we provide the process for a TSV design solution that leverages intrinsic thermo-mechanical properties of polymer-coated via sidewalls and thus a vertical interconnect type that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between silicon substrate and the interfacing metal.



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