Integrated Tools and Systems to Improve 3DI ManufacturabilityAuthors: Sony Varghese, Ahmed H. Abdelnaby, Jonathan S. Hacker
Company: Micron Technology, Inc.
Date Published: 11/11/2014 Conference: IWLPC (Wafer-Level Packaging)
To achieve high die yield, and hence minimal yield loss related to the via reveal process, it is important to understand the requirements and specifications for via reveal uniformity. This applies to current and future 3DI technologies. A systematic analysis for sources of variation from TSV etch, silicon grind, and silicon etch was completed to understand trends and patterns in variations. The results provided justification for the number of steps and the type of control needed on existing tools to meet the via reveal uniformity specifications. As expected, increased time and cost are needed to meet more stringent specifications. Based on the analysis and through experience gained from processing thousands of 3DI wafers over the past few years, we propose ideas for integrated tools and systems that are capable of adapting to process variations, while reducing cost and cycle times to achieve via reveal uniformity targets.
3DI, TSV reveal, Grind, CMP, Tool integration
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