IWLPC (Wafer-Level Packaging) Conference Proceedings

Integrated Tools and Systems to Improve 3DI Manufacturability

Authors: Sony Varghese, Ahmed H. Abdelnaby, Jonathan S. Hacker
Company: Micron Technology, Inc.
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Three Dimensional Interconnect (3DI) technologies, such as Hybrid Memory Cube (HMC) that use Through-Silicon Vias (TSV), are now being generally acknowledged as one of the technologies that will help stave off the challenges brought up by the limitations in shrinking memory technology nodes. As with most developing technologies, 3DI has several challenges in the areas of integration and manufacturability. One of the many challenges in manufacturability is to keep costs down as driven by the number of steps in the process flow and the number of unique process tools that are needed. One example is the process of revealing TSVs uniformly across the wafer as well as from wafer to wafer. Currently, this is achieved using multiple steps such as coarse grind, Chemical Mechanical Planarization (CMP), and either wet or dry etch. The complexities of having to manage sources of variations coming from multiple processes such as TSV etch, temporary wafer bond, grind, CMP and wet or dry etch to achieve uniform via reveal requires the need for tools and control systems capable of minimizing variations.

To achieve high die yield, and hence minimal yield loss related to the via reveal process, it is important to understand the requirements and specifications for via reveal uniformity. This applies to current and future 3DI technologies. A systematic analysis for sources of variation from TSV etch, silicon grind, and silicon etch was completed to understand trends and patterns in variations. The results provided justification for the number of steps and the type of control needed on existing tools to meet the via reveal uniformity specifications. As expected, increased time and cost are needed to meet more stringent specifications. Based on the analysis and through experience gained from processing thousands of 3DI wafers over the past few years, we propose ideas for integrated tools and systems that are capable of adapting to process variations, while reducing cost and cycle times to achieve via reveal uniformity targets.

Key Words: 

3DI, TSV reveal, Grind, CMP, Tool integration

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