Cost Comparison of Embedded Die Packaging and Wafer Level Packaging
Authors: Chet Palesko and Amy Palesko Company: SavanSys Solutions LLC Date Published: 11/11/2014
IWLPC (Wafer-Level Packaging)
Abstract: This paper will compare and contrast the packaging cost and key cost drivers for embedded die packaging and wafer level packaging. This comparison focuses specifically on fan-out wafer level packaging (FOWLP), due to the IO count limitation of fan-in wafer level packaging. Key activity costs and total cost are both presented across a range of die and package sizes. An analysis of the cost of cumulative yield loss is presented for both technologies, comparing them to flip chip. A sensitivity analysis on key cost drivers is also included.