IWLPC (Wafer-Level Packaging) Conference Proceedings


Interposer Based Wide IO Processor Integration

Authors: Andy Heinig, Robert Fischbach, and Michael Dittrich
Company: Fraunhofer Institute for Integrated Circuits, Design Automation Division
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. In this paper we look at interposer-based and stacked solutions to integrate processor and memory into a high performance system. The comparison reveals the current advantages of interposer-solutions. This is underlined by thermal and technological considerations. Even though physical design tradeoffs are existent, we show an actual implementation of the chosen technology.

Key Words: 

3D integration, interposer, WideIO, thermal simulation, technology comparison



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