IWLPC (Wafer-Level Packaging) Conference Proceedings

Panel Based Fan Out Packaging to Reduce Cost

Authors: Klaus Ruhmer, Philippe Cochet, and Roger McCleary
Company: Rudolph Technologies, Inc.
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)

Abstract: As the semiconductor industry is maturing, the reign of Moore's Law has come to an end as well. New approaches beyond scaling down transistors have taken over the burden of continued and rapid performance growth and cost reduction.

Embedded Wafer Level Ball Grid Array (eWLB) provides a robust packaging platform supporting very dense, multilayer interconnection of multiple die at low-profile, lowwarpage and high yield. The use of these embedded fan-out wafer level packaging (FO-WLP) packages in a side-by-side configuration is an effective alternative to stacked package configurations. These fan-out packages can also be utilized as the base for 3D through silicon via (TSV) packages. Last but not least, FO-WLP enables the cost effective combination of dissimilar semiconductor technologies such as analog, digital and memory–all based on known-good-die (KGD). This is especially critical for high-performance system-in-package solutions which are used in high-end mobile devices as well as other leading edge applications.

Most recently, a new trend in FO-WLP can be observed. The industry is considering the use of large area rectangular panels rather than round, reconstituted wafers. This approach offers fundamental cost advantages due to economy of scale. Depending on panel size, a significantly large number of devices can be processed on a single substrate. In addition, the inherent inefficiencies with regards to surface area related to the round shape of reconstituted wafers can be avoided when rectangular or square panels are used. Opposite to that, the equipment infrastructure within the advanced packaging supply chain today is mainly based on processing 300mm round wafers and substrates. New equipment which can process these large panels is required. Although most of these process tools are readily available from the flat panel display industry, some of the typical advanced packaging process requirements such as thick resist lithography and copper electroplating require the development of some new equipment capabilities.

This paper analyzes the die per hour throughput benefits when processing large panels rather than round reconstituted wafers. It specifically highlights the cost advantages of large area lithography compared to a wafer-based approach. At the same time, potential challenges related to lithography and other process steps are being discussed.

Key Words: 

Fan-Out packaging, eWLB, Advanced Packaging Lithography

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