IWLPC (Wafer-Level Packaging) Conference Proceedings

High Resolution 3D X-Ray Microscopy for the Development of Wafer Level Packaging and 3D IC Integration

Authors: Allen Gu, Ph.D., Raleigh Estrada, Bruce Johnson, Gabe Guevara
Company: Carl Zeiss X-ray Microscopy and Invensas Corporation
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Process development and control is becoming more challenging as adoption of 3D IC packaging and 2.5D interposer technology increases in the semiconductor industry. The interconnecting building blocks, such as TSVs, micro-bumps, and pillars, are more densely populated in circuits and structures are becoming more miniaturized. Furthermore, the majority of new interconnecting architectures have utilized the vertical integration technique in which multiple chips are stacked vertically to improve integration density by shorter communication routes.

Structural characterization of the interconnecting elements, such as through silicon vias (TSVs), are of importance to circuit electrical functionality and reliability. Electrical behaviors, i.e. impedance and capacitance, depend on TSV pitch, diameter, and slope, etc. Infrared and visible light interferometry offers metrology solutions for surface TSVs and connected bumps. However, they do not provide enough subsurface detail to uncover subtle structural defects or misalignment of TSVs. Hence, as the process proceeds and devices are stacked vertically, these techniques become less useful because structures of interest are buried deep and most interconnecting materials are made of metals that are opaque to visible and infrared lights.

Key Words: 

non-destructive, 3D X-ray microscopy, XRM, failure analysis, virtual cross-sectioning, intact wafers, microCT, 2D X-ray, high resolution, high contrast, TSV, voids, bumps, cracks, BGAs, tomography, geometric magnification, optical magnification, large working distance

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