IWLPC (Wafer-Level Packaging) Conference Proceedings


High Throughput Wafer Edge Inspection and Monitoring for Advanced Wafer Level Packaging

Authors: Rohit Bhat, Heiko Eisenbach, Marc Filzen, Prashant Aji, Youxian, Wen, Sumant Sood, Thomas Uhrmann, Julian Bravin, Jürgen Burggraf
Company: KLA-Tencor and EV Group
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Some of the essential process steps in the 2.5/3D process flow include temporary bonding, thinning, and eventual de-bonding of the thinned device wafer from the carrier substrate. Edge chips, micro-cracks, edge delamination and total thickness variation (TTV) on the device wafers pose significant challenges during the temporary bonding process flow. Such defects propagate during subsequent back-end-of-line (BEOL) process steps and can result in significant yield loss.

In this paper, we present results from an edge inspection and metrology system for wafer level packaging applications that simultaneously captures 5mm of the wafer top side, wafer edge and 5mm of the wafer bottom side in one scan. The edge inspection system uses multiple detection channels for accurate and fast defect binning and provides 0.5 micrometers sensitivity. The paper focuses on critical inspection and metrology use cases from wafer level packaging and 2.5/3D integration for defect reduction and subsequent yield improvement.

Key Words: 

Wafer edge, Edge inspection, edge metrology, 3DIC, WLP



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