IWLPC (Wafer-Level Packaging) Conference Proceedings


Analytical and Experimental Studies of 2.5D Silicon Interposer Warpage: Impact of Assembly Sequences, Materials Selection and Process Parameters

Authors: Laura Mirkarimi, Ron Zhang, Akash Agrawal, Hala Shaba, Bong-Sub Lee, Rajesh Katkar, Ellis Chau and Sitaram Arkalgud
Company: Invensas Corporation
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations. To this end, extensive thermo-mechanical simulations were performed to conduct virtual design of experiments (DOEs) with variables such as substrate and molding material properties, component dimensions, process temperatures, and assembly process step sequence. Our prototype package has a silicon interposer (27mm x 19mm), two micro-bump dies (10mm x 12mm) and a substrate (40mm x 40mm). The thermal mechanical properties of the materials used in our simulations were experimentally measured to enhance the accuracy of the models. Using a step by step simulation methodology, over 40 simulations were completed to find the optimized assembly process and package structure. The simulation results are compared with measurements to establish the validity of the models prior to further design optimizations. Our results identified multiple paths to obtain successful assembly scenarios yielding quality packages and the dependencies on process variables and materials selection. Due to the variety of applications for 3D-IC, we see value in maintaining a tool set of several assembly manufacturing techniques. We provide the specific guidelines for building package assemblies similar to our prototype parts with a warpage less than 100 micrometers.

Key Words: 

Finite element analysis, warpage, assembly process, interposer



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