IWLPC (Wafer-Level Packaging) Conference Proceedings

300mm Wafer-Scale Through-Silicon Via (TSV) Process with Optimized Backside Reveal and Planarization Methods

Authors: Seth Kruger, Douglas La Tulipe, Matt Smalley, John Mucci, Douglas Coolbaugh
Company: SUNY Polytechnic Institute
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The Through Silicon Via (TSV) is a key feature in the implementation of 2.5 and 3D integration approaches. The fabrication of TSVs requires unique processing steps that are not typical in a standard back-end-of-line (BEOL) CMOS integration flow. Examples are wafer bonding, wafer thinning and backside TSV reveal. It has been shown that excessive total thickness variation (TTV) of the remaining Si substrate results in nonuniform TSV reveal heights and poses severe integration challenges [1-4]. The TTV of the thinned Si wafer is difficult to control, with contributions from RIE lag, variations in bond layer thickness, and non-uniform Si removal during the wafer grinding and TSV reveal processes. This study focuses on reducing and correcting Si TTV with post wafer bonding processes. A comprehensive tool evaluation eliminated Si cracking during wafer thinning and an optimized high yield TSV reveal process was developed with < 1.5 µm TSV height variation across a 300 mm wafer.

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