IWLPC (Wafer-Level Packaging) Conference Proceedings


Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production

Authors: Carolyn Short, Chris Jones, Dave Thomas and Keith Buchanan
Company: SPTS Technologies Ltd.
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: This paper highlights a number of challenges and solutions developed to meet the needs of MEMS manufacturers using 3D packaging for low I/O count devices.

Various process steps, such as, TSV etch, dielectric liner deposition, barrier/seed PVD have been developed and optimized to increase electrical performance, increase throughput and reduce costs for volume production.

In particular, various silicon etch processes have been developed to create a wide range of TSV profiles, both tapered (allowing relatively simple deposition processes) and vertical (reducing real estate). Unique endpointing techniques have also been proven in production for both tapered and vertical vias.

Low temperature PECVD is also a key process, for depositing via dielectrics onto bonded wafers with a low temperature (<200°C) threshold.

Finally, this paper illustrates some of the challenges regarding barrier/seed deposition using conventional PVD, and ionized PVD and how technologies such as MOCVD may be useful.

Key Words: 

MEMS Packaging, TSV etch, silicon DRIE, low temperature PECVD, high aspect ratio PVD



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819