IWLPC (Wafer-Level Packaging) Conference Proceedings

Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production

Authors: Carolyn Short, Chris Jones, Dave Thomas and Keith Buchanan
Company: SPTS Technologies Ltd.
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)

Abstract: This paper highlights a number of challenges and solutions developed to meet the needs of MEMS manufacturers using 3D packaging for low I/O count devices.

Various process steps, such as, TSV etch, dielectric liner deposition, barrier/seed PVD have been developed and optimized to increase electrical performance, increase throughput and reduce costs for volume production.

In particular, various silicon etch processes have been developed to create a wide range of TSV profiles, both tapered (allowing relatively simple deposition processes) and vertical (reducing real estate). Unique endpointing techniques have also been proven in production for both tapered and vertical vias.

Low temperature PECVD is also a key process, for depositing via dielectrics onto bonded wafers with a low temperature (<200°C) threshold.

Finally, this paper illustrates some of the challenges regarding barrier/seed deposition using conventional PVD, and ionized PVD and how technologies such as MOCVD may be useful.

Key Words: 

MEMS Packaging, TSV etch, silicon DRIE, low temperature PECVD, high aspect ratio PVD

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