Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume ProductionAuthors: Carolyn Short, Chris Jones, Dave Thomas and Keith Buchanan
Company: SPTS Technologies Ltd.
Date Published: 11/11/2014 Conference: IWLPC (Wafer-Level Packaging)
Various process steps, such as, TSV etch, dielectric liner deposition, barrier/seed PVD have been developed and optimized to increase electrical performance, increase throughput and reduce costs for volume production.
In particular, various silicon etch processes have been developed to create a wide range of TSV profiles, both tapered (allowing relatively simple deposition processes) and vertical (reducing real estate). Unique endpointing techniques have also been proven in production for both tapered and vertical vias.
Low temperature PECVD is also a key process, for depositing via dielectrics onto bonded wafers with a low temperature (<200°C) threshold.
Finally, this paper illustrates some of the challenges regarding barrier/seed deposition using conventional PVD, and ionized PVD and how technologies such as MOCVD may be useful.
MEMS Packaging, TSV etch, silicon DRIE, low temperature PECVD, high aspect ratio PVD
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