Thermal Resistant Thin Wafer Support Technology for 3DIC
Authors: Alman Law, Jared Pettit, Alex Brewer, and John Moore Company: Daetec, LLC Date Published: 11/11/2014
IWLPC (Wafer-Level Packaging)
Abstract: High temperature processing in microelectronic operations includes plasma deposition, dielectric curing, and annealing. Engineering polymers are chosen based upon sufficiently high Tg. Few materials can withstand temperatures beyond 400C without suffering some level of degradation. With careful formulating, composite coatings can resist temperatures >500C with limited outgas and have demonstrated coatings that support processes at 600C. While processes that involve temporary wafer bonding operate much lower, many polymers can exhibit serious processing problems as outgassing and loss of the materials’ properties. Many barriers exist to manufacturing integration, including high cost, poor yield, and poor throughput. As the demand continues for smart phones, 3DIC becomes a required process to manufacturing the devices needed to operate these units. One such technology, DaeBond 3DTM, supports processing temperatures to 350C while bonding near room temperature and de-bonding in a batch process while thinned device wafers remain affixed to film frames . This paper will discuss several examples of thermal resistance for 3DIC processing.