IWLPC (Wafer-Level Packaging) Conference Proceedings


Development Done on Device Bonder to Address 3D Requirements in a Production Environment

Authors: Pascal Metzger, Ph.D., Joseph Macheda, Michael D. Stead, Keith A. Cooper
Company: SET Corporation and SET North America
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Among competing technologies to shrink the total size of electronic systems, 3D integration incorporating through-silicon-vias (TSVs) is one of the most promising candidates. But despite progress in a number of key process steps, brought about through research efforts conducted at many corporations and institutes and widely reported at technical conferences, cost of ownership remains a major hurdle to adopting 3D integration in high-volume manufacturing (HVM).

Key to the success of 3D integration will be the ability to accurately align and bond devices with aggressive feature sizes. Whether the methodology involves die-to-die, dieto- wafer or even wafer-to-wafer bonding, novel challenges in the areas of bonding metallurgy, materials handling, alignment methods and thermal management must be met simultaneously in order to realize high-performance electronic systems in production.

Through partnerships and equipment installations at several leading research institutes around the world, certain technological advancements have emerged, including:

CEA-LETI, Grenoble, France has presented successful die-to-wafer bonding using 4 µm diameter Au-coated microtubes at 10 µm pitch inserted into pads, as well as a molecular attachment bonding method developed within the Proceed project, Sematech USA and IMEC Belgium have each developed a hybrid collective bonding scheme where accurate die-to-wafer initial bonding is followed by gang bonding to finalize many bonds in parallel, IME Singapore has developed several solder compositions and methods to create reflow bonding process options.

To realize these and other process options in an HVM environment, the device bonder must incorporate high accuracy placement with high parallelism control at elevated temperatures with high throughput, while accommodating a wide variety of device sizes and thicknesses. Furthermore, many bonding materials will require surface preparation and protection methods either ex-situ, in-situ or both.

This paper will explore the above challenges in 3D HVM and will present solutions and trade-offs using a systems-level approach.

Key Words: 

High precision flip-chip, TSV, 3D integration, HVM



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