IWLPC (Wafer-Level Packaging) Conference Proceedings


Reconstituted Big-Chip LEDs on Multi-Layer Interconnects for High-Brightness Lighting

Authors: Liang Wang, Gabe Guevara, Grant Villavicencio, Roseann Alatorre, Hala Shaba, Rey Co, Eric Tosaya
Company: Invensas Corporation
Date Published: 11/11/2014   Conference: IWLPC (Wafer-Level Packaging)


Abstract: LEDs have been the key driving force to revolutionize general lighting with much higher efficiency and longer lifetime. However higher brightness requires LEDs to be operated at higher current density which results in efficacy degradation due to droop behavior and thus higher power loss into heat and shorter lifetime. Therefore a large chip size is preferable because with larger chip size, higher brightness can be achieved at much lower current density which leads to less degradation of efficacy. However fabricating large-size LEDs hinders HVM due to significant yield loss. In this paper we propose a scalable approach to enable larger chip sizes for manufacturing high efficacy & high brightness LEDs at high yield and low cost. Known- Good-Dies of small-size LEDs are reconstituted on multilayer interconnects to achieve big chip size with minimal yield loss. Flip chip packaging is chosen due to its advantage of full front-side emission, maximized aperture ratio, compact form factor, higher integration density and ease of wafer level process. The substrates for flip chip packaging of LED chips are made of Si which was selected due to its relatively high thermal conductivity (149 W/m/K) and ease of fabrication with standard semiconductor processes. Multi-layer interconnects are patterned over the Si substrate with solder bumps built over the passivation openings for flip-chip assembly of multiple LED dies into a single lighting chip of uniform optics. The multi-layer dielectric stack of the substrate is designed to form dielectric mirror maximizing the reflection of emitted light back into the LED side for improved light output. Given the minimal thickness of the device stack, the key bottleneck for thermal dissipation resides in the packaging structure and its interface to the device stack. We address this key challenge with a novel wafer-level packaging structure of metal contacts in the form of a surrounding wall integrated into the device stack, which enables maximal thermal dissipation rate from the active device stack to substrate while allowing high aperture ratio and optimized light output.

Key Words: 

LED lighting, big chip, flip-chip assembly, multi-layer interconnect, light extraction



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