SMTA International Conference Proceedings

Package on Package Module Assembly Process Development

Authors: Chuan Xia, Charles Gui and Scott Priore
Company: Cisco Systems, Inc.
Date Published: 9/28/2014   Conference: SMTA International

Abstract: Package technology has been advanced significantly over the past several years, shifting from conventional components and direct board level assembly to chip or package level system integration. Two major commonly used approaches are System-on-Chip (SoC) and System-in-Package (SiP). Package-on-Package (PoP) that integrates processor in the bottom package and memory in the top package into a single 3D package is one of the promising SiP solutions. In addition to decreasing component pitch, utilization of the vertical space by stacking packages has found wide acceptance by electronic industry. Pb-free PoP technology represents one of the latest advancements in vertical electronics packaging integration and has become the preferred technology for mobile hand held electronics.

All fine pitch components are assembled on the module and interconnected to the main board via BGA interface on the bottom of module in order to drive cost down by reducing the HDI interposer size and removing interface connectors. By changing the module top side and mother board designs, we can add more features and have more flexibility for products.

It is not common for board level assembly factory to have capability of solder ball attachment process. Therefore, the work offers great technical challenges on optimizing process material and process parameters. It is also the first time for Cisco to assemble such fine pitch BGAs and develop solder ball attachment process.

This paper describes process material selection, PoP module assembly process development and solder ball attachment process qualification. Detailed DOE and thermal cycle test have been carried out to verify assembly processes.

Key Words: 

Package on package (PoP) module, Fine pitch component, Flux dipping process, Solder ball attachment process, High density interconnection (HDI) interposer, Design of experiments (DOE)

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