A High Dense Organic Interposer with Fine Feature Size for Advanced Packaging ApplicationsAuthors: Christian Romero, Jeongho Lee, and Youngdo Kweon
Company: Samsung ElectroMechanics Co., Ltd.
Date Published: 9/28/2014 Conference: SMTA International
The next generation substrate design rules require a process capability with less than 50um pitch to accommodate leading-edge mobile applications such as wide I/O memory. Also, the expanding use of multi-core processors to mitigate power, the need for increasing bandwidth, the chip-package interconnect reliability issues are limiting factors for the present conventional 2D packaging methods therefore there is presently a strong need to develop new packaging architectures to allow device scaling to continue. There are growing interest in several technology, such as 3D packaging using Si-TSV interposer as alternatives to scaling with specific industrialization goals but cost viability remains unclear.
Given these challenges, organic-based interposers seem to be the most practical intermediate solution today for heterogeneous packaging of highly functional ICs with high I/O-counts because of its already well established ecosystem, lower cost and proven level of reliability.
This paper addresses the design and fabrication of an advanced organic interposer for high I/O-count, ultra fine-pitch ICs. Our concept uses a novel process for the redistribution layers that can demonstrate ultra fine line interconnects with width/space below 5um with microvias with pitch below 50um which can be effective solution for high density routing. This feature enables the ICs to be attached directly to the substrate therefore eliminating the need for a silicon interposer in the conventional 2.5D package architecture. The final package will provide low profile structure with better reliability and cost efficiency. We will present our various feasibility results of electrical/mechanical performance obtained from our fabricated test vehicles.
Interposer, organic, fine-pitch stacked vias, PDN, signal integrity, high density I/O, Die Interconnects
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