FLIP-CHIP / CSP ASSEMBLY RELIABILITY AND SOLDER VOLUME EFFECTS
Author: Jean-Paul Clech Company: EPSI Date Published: 8/23/1998
Surface Mount International
Abstract: With accelerated test data suggesting that most flip-chip (FC) and Chip Scale Package (CSP) assemblies on organic boards have shorter lives than conventional or area-array Surface Mount (SIN) assemblies, solder joint reliability is possibly being pushed to the limits. The reliability of FC and CSP assemblies cannot be taken for granted, thus requiring careful interpretation of test results and more accurate means of extrapolating test failure cycles to field conditions. This paper presents the extension of the Solder Reliability Solutions (SRS) model  to soldered FC and CSP assemblies. The model is validated by failure data from over fifty accelerated thermal cycling tests, including FC, ceramic CSP and micro-BGAt solder joint failures. For FC assemblies, underfill shear strain predictions nicely fit shear strain distributions obtained by moire interferometry and predicted die stresses are in agreement with stress sensor measurements. Last, the analysis of FC test results demonstrates the impact of solder joint volume on attachment reliability and a solder volume correction factor is introduced in the SRS model. The effect of solder volume on solder joint fatigue is further validated with ceramic CSP failure data. Keywords: Solder joint fatigue, predictive modeling, design-for-reliability, flip-chip / chip-scale assemblies.