Eliminating BTC Voiding on the Fly: In-Production Optimization Techniques
Authors: Rafael Padilla, Kazuyori Takagi, Ko Inaba, Satoru Akita, Derek Daily, Tokuro Yamaki, Hideki Mori, Tomoyasu Yoshikawa and Masato Shimamura Company: Senju Comtek Corporation and Senju Metal Industry Co., Ltd. Date Published: 5/13/2014
ICSR (Soldering and Reliability)
Abstract: Various quad-flat no-lead (QFN) packages, land grid arrays (LGA) and ball grid arrays (BGA) are being combined on a number of products with ever increasing component densities and complexities. The bottom terminated component’s (BTC) small footprint, low cost, and excellent electrical as well as thermal performance make them a preferred solution for a wide range of applications. The purpose of this study is to determine which in-process optimization techniques may be utilized to reduce voids and HiP type defects on complex assemblies. Techniques such as reflow profile adjustment and stencil design modifications will be explored, as they are applied to a 6 layer Cu-OSP test vehicle built with multiple devices including QFN, LGA, BGA, dPAK and other components. A common SAC alloy, Halogen-Free, No-Clean, Type 3 solder paste was used for these tests.