Alignment and Performance for Chip-To-Chip Communication
Authors: Meihui Guo, Jen-Feng Huang, and Yu-Jung Huang Company: National Sun Yat-sen University and I-Shou University Date Published: 2/11/2014
Pan Pacific Symposium
Abstract: Using capacitive-based chip-to-chip signaling in large-scale systems offers an interesting tradeoff between design and packaging complexity versus power consumption and performance. Placing chips together in close proximity offers low energy per-bit costs and high I/O density, and therefore enables off-chip bandwidth levels far beyond those offered by traditional packaging and I/O technologies. Much of the previous published work on capacitive Proximity I/O has focused on mechanical methods for accurate chip alignment. In this paper we discuss some system design considerations unique to Proximity I/O. We analyze the transmission signal of coupling pads at different configurations. The High Frequency Structure Simulation (HFSS) technique is used to simulate the signal data of two pads with overlapping area ranging from 0% (completely non-overlapping) to 100% (complete overlaping). The coupling effects of the signal are then statistical analyzed. The objective of this work is to investigate the chip placement configuration which can result in the best signal quality.