Optimization of Leveler Concentration to Minimize the Contamination of Copper in Via Filling
Authors: Ki-Tae Kim and Jae-Ho Lee Company: Hongik University Date Published: 2/11/2014
Pan Pacific Symposium
Abstract: Electroplating copper via filling is one the most important technology in stacking interconnection of SiP. The requirement for success of via filling is its ability to fill via holes completely without producing voids and seams. Defect free via filling was obtained optimized plating conditions such as current mode, current density and additives. However, by products stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the characterization of levelers (JGB, MV, DB) on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. Prior to via filling, levelers are analyzed by cyclic voltammetry, galvanostatic & potentiostat plots. The aspect ratio of via is important as well as the size of via. Different aspect ratio and different size of via gave the different optimized conditions. The cross sectional and surface morphologies of via were examined using FESEM.