Advances in Etch and Deposition Technologies for 2.5 and 3D BEoL Processing
Authors: Keith Buchanan, Dave Thomas, Hefin Griffiths, Kathrine Crook, Daniel Archard, Mark Carruthers, Steve Burgess, and Stephen Vargo Company: SPTS Technologies Ltd. Date Published: 2/11/2014
Pan Pacific Symposium
Abstract: This paper discusses the optimisation of plasma etch and deposition processes used in interposer and "via middle" schemes to reveal and passivate through-silicon vias [TSV] on the back sides of 300mm silicon wafers, thereby enabling subsequent contact, bonding and stacking processes. A dual source inductively-coupled etch system with innovative insitu endpoint control enables highly uniform silicon etch, suitable for high volume production. Following the etch step, low temperature (<180°C) plasma-enhanced chemical vapour deposition (PECVD) is used to deposit a silicon nitride (SiN) / silicon oxide (SiO) stack to provide electrical isolation, bow compensation and mechanical support of the revealed vias.
3D Packaging, via reveal, low temperature PECVD, silicon etch, in-situ endpoint