IWLPC (Wafer-Level Packaging) Conference Proceedings


Cost Comparison Of Multi-Die Fan-Out Wafer Level Packaging And 2.5D Packaging With A Silicon Interposer

Authors: Chet Palesko, Amy Palesko; and E. Jan Vardaman
Company: SavanSys Solutions LLC and TechSearch International, Inc.
Date Published: 11/5/2013   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Miniaturization and performance requirements are driving product designers to use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity cost and yield will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs.

Key Words: 

2.5D, 3D, TSV, FOWLP, Cost, Interposer



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