IWLPC (Wafer-Level Packaging) Conference Proceedings

Inspection And Metrology Solutions For Copper Pillar High Volume Manufacturing

Author: Rajiv Roy
Company: Rudolph Technologies
Date Published: 11/5/2013   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The Semiconductor industry has been accelerating the adoption of copper pillar bumping. Copper pillar as an interconnect has been used for Flip-Chip Ball Grid Arrays (FC-BGA) for a few years. Fine pitch copper pillar is also considered a key interconnect technology for the emerging TSV applications and several companies have announced it as an interconnect between packages for POP (Package on Package) applications. Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set apply to copper pillar bumping , not just for standard thickness wafer, but also for thinned bonded and warped wafers as when copper pillars are the interconnect on one side of wafer with Through-Silicon Vias (TSV). Rudolph will discuss an inspection system that incorporates multiple metrology sensors to provide complete 2D and 3D measurement and inspection solutions.

Key Words: 

Copper pillar bumping, Inspection, Metrology, Process Control.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819