Interconnect Structure For Room Temperature 3D-IC Stacking Employing Binary Alloying For High Temperature Stability
Authors: Eric Schulte, Matthew Lueck, Alan Huffman, Chris Gregory, Keith Cooper, Dorota Temple Company: SET North America and RTI International Date Published: 11/5/2013
IWLPC (Wafer-Level Packaging)
Abstract: Numerous metal contact stacks have been proposed for 3DIC chip stack assembly. Copper is a popular choice for standoff posts since it is well-characterized and in regular production today. However, since direct Cu-Cu bonding is problematic due to planarity and oxidation issues, many development groups employ a Sn or SnAg solder cap on top of the Cu post, sometimes with a Ni diffusion barrier, to provide bondline compliance and to reduce bonding force and temperature. But this structure still requires reflow bonding temperatures around 250C or thermo-compression bonds around 185C. These thermal excursions consume energy and time, and will induce CTE-driven misalignment and stresses when bonding devices comprised of heterogeneous materials such as InGaAs, InP, or Si. Indium has been proposed as a replacement for Sn to allow room-temperature “cold-welding”, but elemental indium melts at 156C and is not compatible with subsequent solder reflow assembly processes. We propose depositing Ni\In onto the Cu post on one side of the bond interface, and Ni\Ag to the other side to create a metallurgical system which can be bonded at room temperature to create robust mechanical and electrical interconnects. An Atmospheric Plasma process is used to de-oxidize and passivate the In and Ag surfaces, followed by room temperature compression bonding of the In to Ag. Subsequent chip layers can be stacked in the same manner at room temperature without requiring thermal excursions for melting and solidification. Following completion and test of the stacked assembly, solid-state annealing will alloy the In and Ag layers, raising the melt temperature of the In/Ag alloy to above standard solder assembly temperatures. We present details on device fabrication, pre-bond surface preparation, bonding profiles, interconnect yield and preliminary reliability testing for this promising interconnect structure.