Polyimede PCB Embedded With Two Dies In Stacked Configuration
Authors: Koji Munakata, Nobuki Ueta, Masahiro Okamoto, Kumi Onodera, Kazuhisa Itoi, Satoshi Okude and Osamu Nakao; and Jon Aday and Theodore (Ted) G. Tessier Company: Fujikura Ltd. and Flip Chip International, LLC Date Published: 11/5/2013
IWLPC (Wafer-Level Packaging)
Abstract: We have developed a polyimide-based embedded wiring board in which multiple dies are embedded in a 3D stacked configuration based on WABE (Wafer and Board level Embedding) technology, which has been used for a single die embedding. With this technology, the embedded dies are optimally processed by a WLP (wafer level packaging) process for embedding application, which have copper pad and are thinned down to 0.085mm. Next, each die is sandwiched between polyimide flex films on which copper circuits are formed with adhesive materials. Then, the dies are placed in different layers and occupy the same projected area so that a highly integrated structure can be achieved. This time, the multi-die embedded board in a stacked configuration was produced by a two-step lamination process. First, a single die embedded wiring board was fabricated by our WABE process. Regarding this fabricated board as a single circuit film, we performed the second laminating process in the same manner using the second die. The board included two WLP dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The measured thickness of this fabricated board was 0.55 mm. This was about the same size as that of a conventional non-embedded build-up board. Electrical connections between circuit layers including embedded dies were established by a reliable conductive paste. We have performed moisture soak reflow tests on test vehicles and verified that they endured the conditions compliant with JEDEC level2.