Warpage Mitigation Processes In The Assembly Of Large Body Size Mixed Pitch BGA Coreless Packages For Use In High Speed Network ApplicationsAuthors: John Savic and Weidong Xie; Nokibul Islam, Park Gun Oh, Raj Pendse and KyungOe Kim
Company: Cisco Systems and STATS ChipPAC
Date Published: 10/13/2013 Conference: SMTA International
A test vehicle was developed using a 22x18mm^2, 40nm Daisy Chain die placed onto a 45x45mm^2, 8+1 coreless substrate with mixed pitch BGA footprint and BGA-side capacitors. Processes were developed to optimize assembly yield and package reliability. Key assembly materials were selected for optimum yield and high thermo-mechanical reliability. Substrate material stack-up and design were varied for further optimization and validation of thermal mechanical reliability models. As a result, critical factors impacting warpage were identified and modeling tools were refined to predict substrate.
This paper describes the assembly processes, substrate BOM selection and design strategies adopted for mitigating warpage for coreless package sizes up to 45x45mm. Additionally, L1 thermal mechanical reliability results and key factors for establishing valid models will be discussed.
Coreless, mpBGA, warpage, ASIC, assembly process.
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