SMTA International Conference Proceedings


Warpage Mitigation Processes In The Assembly Of Large Body Size Mixed Pitch BGA Coreless Packages For Use In High Speed Network Applications

Authors: John Savic and Weidong Xie; Nokibul Islam, Park Gun Oh, Raj Pendse and KyungOe Kim
Company: Cisco Systems and STATS ChipPAC
Date Published: 10/13/2013   Conference: SMTA International


Abstract: Next generation high speed network ASIC packages require perpetually larger and thinner packages to meet functionality and electrical performance requirements. Opportunities for highly integrated MCM’s and 2.5D/3D Si interposer packages are emerging to meet long-term performance needs, but for near-term, single chip ASIC applications, thinner packages utilizing thin substrates are an absolute requirement for the high end network market. Achieving both increased margins in the power delivery network and increased functionality in next generation 25/28GHz ASIC applications requires highly efficient (thin, minimal discontinuities, opportunities for enhanced decoupling), low loss package designs with package sizes up to 60x60mm. Coreless substrate based packages offer an excellent opportunity for low loss/low inductance package designs, but have consistently failed to be available at the necessary body sizes due to assembly and warpage concerns. The work presented in this paper describes key factors for mitigating warpage and identifies optimum processes, and materials for manufacturing large body size coreless substrate packages, especially for the high end network market.

A test vehicle was developed using a 22x18mm^2, 40nm Daisy Chain die placed onto a 45x45mm^2, 8+1 coreless substrate with mixed pitch BGA footprint and BGA-side capacitors. Processes were developed to optimize assembly yield and package reliability. Key assembly materials were selected for optimum yield and high thermo-mechanical reliability. Substrate material stack-up and design were varied for further optimization and validation of thermal mechanical reliability models. As a result, critical factors impacting warpage were identified and modeling tools were refined to predict substrate.

This paper describes the assembly processes, substrate BOM selection and design strategies adopted for mitigating warpage for coreless package sizes up to 45x45mm. Additionally, L1 thermal mechanical reliability results and key factors for establishing valid models will be discussed.

Key Words: 

Coreless, mpBGA, warpage, ASIC, assembly process.



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