SMTA International Conference Proceedings

Optimizing Assembly Of QFNs

Authors: Brook Sandy-Smith and Seth Homer
Company: Indium Corporation
Date Published: 10/13/2013   Conference: SMTA International

Abstract: There has been a lot of work done recently in the electronics industry to minimize voiding in solder joints, especially in the thermal pad connections under bottom termination components, such as the QFN. Through all of this work, many strategies have been proposed that improve voiding performance. However, no single solution has eliminated voiding at this time. Successfully proven approaches have included reflow profiling, stencil design, thermal pad design, thermal pad patterning, material selection, addition of solder preforms, etc.

In previous work, it has been observed, that some of these proven approaches impact the integrity of QFN assemblies more than just the amount of voiding. For instance, the size and placement of vias in these thermal pads can be optimized to minimize voiding and help with heat dissipation. However, these vias can also draw solder volume away from the solder joint, resulting in a large variance in voiding results, as well as in the loss of standoff height. In order to further define “best practices to minimize QFN voiding”, several combinations of proven approaches were tested on a user-defined test board and fully analyzed to gain understanding of QFN performance, in addition to typical voiding results.

Key Words: 

voiding, thermal pad design, QFN assembly, low-voiding, solder paste

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