A Multi-Level Finite Element Study To Analyze The Chippackage- Interaction For Cu/Low-K Interconnects
Authors: Hardik Parekh, Fahad Mirza, Samip Shah, and Dereje Agonafer Company: University of Texas at Arlington Date Published: 10/13/2013
Abstract: In this era of miniaturization Cu/low-k interconnect layers in the Back-End-of-Line (BEoL) is the most obvious choice for the integrated circuit (IC) manufacturer. RC delay has been considerably lower after replacing Al with Cu. low-k and ultra-low-k increases the device performance through RC delay reduction and further allows the manufacturing of compact ICs. BEoL miniaturization with the technology node has reached a level where its thermo-mechanical integrity has become a serious concern. Low-k material has lower mechanical strength and lower adhesion characteristic compared to other dielectric materials (SiO2) which makes it necessary to assess and mitigate its thermo-mechanical characteristic under different loading conditions (Reflow and thermal cycling, etc.,). CTE mismatch between various components leads to warpage, fracture and cracks in solder bumps and Back End of Line (BEoL). Therefore BEoL damage is a major hindrance in reliability of the package. Purpose of the study is to analyze the thermo-mechanical behavior of the Cu/low-k interconnect region using a multilevel finite element technique. Sub modeling technique has been leveraged to focus on the stress-strain behavior of the Cu/low-k region. This study investigates the effect of the solder bump footprint and the substrate thickness on the reliability of the Cu/low-k region. This study will provide a platform for future study and help chip designer to standardize solder bump dimensions.