Authors: Lilia May, Dudi Amir, Srinivasa R. Aravamudhan, Garrett D.Cogburn, Christopher Kovalchick, Rajen S. Sidhu, Suddhasattwa Nad, Wade Hezeltine Company: Intel Corporation and Oregon State University Date Published: 10/13/2013
Abstract: Component bake is commonly used by the electronics manufacturing industry to remove moisture from packages that exceed IPC/JEDEC floor life exposure time requirements, J-STD-033C. Excess moisture can result in component cracking and/or delamination of package substrate layers during the reflow cycle, thereby impacting surface mount technology (SMT) assembly yield and product reliability. While the impact of moisture is well understood, the effect of baking on solder joint quality is difficult to identify and quantify. There are many aspects within SMT assembly process and material sets that can induce or minimize formation of solder joint defects, such as Non-Wet Opens (NWO) and Head-on- Pillows (HoP). However, occurrence of these defects has been rarely evaluated with respect to pre-SMT component bake. This paper discusses how the component baking process effects flip chip ball grid array (FCBGA) component warpage and oxidation levels for Sn- 4.0wt%Ag-0.5wt%Cu solder ball metallurgy. The impact of baking time on the generation of solder joint defects will also be investigated and the importance of solder paste selection for improving SMT yields will be emphasized.