Effect Of System Design And Test Conditions On Wafer Level Package Drop Test Reliability
Authors: Tiao Zhou, Ph.D. and Xuejun Fan, Ph.D. Company: Maxim Integrated and Lamar University Date Published: 10/13/2013
Abstract: The effects of system design and drop test (DT) conditions on wafer level package (WLP) DT reliability are studied through DT experiments and finite element analysis (FEA). It is concluded that the failure rate of corner components on JEDEC board is inversely proportional to the corner component distance to the nearest mounting hole. BGA packages mounted in proximity to WLP affect WLP DT performance. A larger BGA mounted directly beneath the WLP significantly improves WLP DT life. However, when the BGA mount location partially overlaps with the WLP, WLP DT life is reduced. In this case the solder joint cracks at the WLP edge away from the BGA are significantly accelerated by the BGA. Face-up drop results in earlier failures for corner components than that in face-down drop. But for the central component group in the JEDEC board, it shows slight better performance.