SMTA International Conference Proceedings


Solder Assembly Solutions For 3DIC Packaging

Authors: Charles G. Woychik Ph.D., Ellis Chau, Sitaram Arkalgud Ph.D., Andrew Cao Ph.D. and Vern Solberg
Company: Invensas Corporation
Date Published: 10/13/2013   Conference: SMTA International


Abstract: 3DIC packaging is transitioning from the lab to commercial adoption. The arrival of the first commercial 2.5D (silicon interposer) product challenges the industry to question; "which parts of the process and supply chain are maturing, and which parts are ripe for reinvention?" The market driver for semiconductor package technology is to increase product functionality and performance without increasing product size. Vertically configured through silicon via (TSV) package technology will address this issue for a broad number of enterprise products but the capabilities and methodologies for processing and joining wafers and semiconductor die elements currently vary a great deal between suppliers.

Two companies in Silicon Valley have joined forces to develop a high volume manufacturing (HVM) process for fine-node 2.5D interposer fabrication. Invensas Corporation, in partnership with AllVia, Inc., a domestic silicon wafer foundry, have concentrated resources to develop microbumped die that will accommodate interconnect schemes exceeding 10,000 I/O. Throughout the development program, extensive computer modeling of the assembly process was used to evaluate different process flows in order to arrive at a high yielding assembly process, and reliable 3D package design. This paper will furnish an overview of TSV joining process development activity and review remaining "choke-points" in those areas in need of reengineering and/or reinvention.

Key Words: 

2.5D, 3D, semiconductor packaging, through silicon via, TSV, die stack, wafer stack.



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