Pan Pacific Symposium Conference Proceedings


Authors: Vern Solberg and Ilyas Mohammed
Company: Invensas Corporation
Date Published: 1/22/2013   Conference: Pan Pacific Symposium

Abstract: Stacking heterogeneous semiconductor die (memory and logic) within the same package outline has compromised test efficiency and overall package assembly yield. Separating and packaging the semiconductor functions into sections for stacking, on the other hand, has proved to be more efficient. Although package-on-package methodology is currently considered a primary assembly solution for the logic and memory applications, the next generation of processors will have increased functionality, more I/O and more complex multiple die memory configurations. This factor has prompted developers to seek a packaging solution that is economical, physically robust and will enable a significant reduction in contact pitch. This paper addresses the primary technological challenges for reducing contact pitch for package-on-package applications with current solder ball interface methodology. The authors follow with an introduction to the ‘Bond-Via-Array’ (BVA) package assembly process, a unique approach for forming smaller and finer pitch contacts on the organic based interposer substrate. The BVA contact forming process utilizes copper wire-bond technology that enables several contact profile variations and can furnish an array configured contact pitch as small as 200µm. This interconnect solution is very economical and lends itself to a wide variety of 3D packaging applications, including multiple-row, area array, fan-in and fan-out configurations.

Key Words: 

Package-on-Package, PoP, Bond Via Array, BVA.

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