Pan Pacific Symposium Conference Proceedings


Authors: K. Weide-Zaage, J. Schlobohm, H. Frémont, A. Farajzadeh, J. Kludt
Company: Leibniz University Hannover and Universite Bordeaux I
Date Published: 1/22/2013   Conference: Pan Pacific Symposium

Abstract: Increasing demand, regarding to advanced 3D-packages and high performance applications, accelerates the development of 3D-silicon integrated circuit, with the aim to miniaturize and to reduce the cost. Due to drastic dimension mismatches between interconnects, through-silicon-vias (TSV), and landing pads, the reliability of the systems and components are affected by thermal and thermal-electrical loads due to high temperature as well as high applied currents. This stress leads to degradation effects like electro- and thermomigration (EM, TM). Mechanical or thermal stress due to coefficient of thermal expansion (CTE) mismatch of the different materials on one hand and induced stress during the flip-chip-packaging process on the other hand can lead to delamination and cracking on the packing side or in the IC’s. Investigations of electro- and thermomigration as well as the mechanical stress concerning the reliability of the through silicon vias, BGA-PoP-Packages as well as µ-bumps which are the most critical areas for the emergence of failure, remains a major concern in reliability studies. Generally measurements are time consuming and expensive and the time-to-market cycle is in the focus of interest too. Due to this, simulations offer a possibility for a fast analysis of weak links and problematical areas in the investigated structures and avoid re-design.

Key Words: 

µ-bump, PoP, migration, TSV, delamination, cracking, reliability

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