Pan Pacific Symposium Conference Proceedings


Three Dimensional Integration Research Focusing on Device Embedded Substrate

Author: Hajime Tomokage
Company: Fukuoka University
Date Published: 1/22/2013   Conference: Pan Pacific Symposium


Abstract: The national research project on 3D integration technology had been carried on in Fukuoka, Japan from 2002 to 2012. The system-in-a-package (SiP) design tools STEERSIP and STEERMEMS, test element group (TEG) chips for evaluating the assembling process, and the evaluation equipment such as scanning electron and laser beams induced current (SELBIC) measurement system have been developed. In 2011, a new research center for 3D semiconductors was constructed, where the main research is on device embedded substrate and silicon interposer with through silicon via (TSV). According to the Japan Electronics Packaging and Circuits Association (JPCA) standard on device embedded substrate EB01 and EB02, the evaluation kits for device embedded substrate are developed in order for device companies to perform function test of embedded devices with the common substrate structure.

Key Words: 

3D integration technology, device embedded, SiP, TSV



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819