CRITERIA FOR HIGH-SPEED MOUNTING OF AREA ARRAY PACKAGES (BGAs, pBGAs/CSPs AND FLIP CHIPS)
Author: Gunter Schiebel Company: Siemens AG Date Published: 4/28/1997
Surface Mount International
Abstract: There is no doubt that future SMT designs will more and more use the advanced packages BGA, pBGA/CSP and flip chip. The key problems with fine pitch QFPs and TSOPS with lead pitches of 0.4 mm and smaller, but even with 0.5 mm, are the low production yields. As long as the pitches of area array packages are not too extreme (e.g. smaller than 200 pm in case of flip chips) the dpm rates after reflow soldering are, compared with classical fine pitch technology at least 10 times better. Another big advantage in terms of overall manufacturing costs are, particularly in case of flip chips, the dramatic PWB real estate savings. Area array packages are also clearly beneficial when it comes to electrical performance. Due to the fact, that in most applications a strong self alignment during reflow soldering occurs, placement accuracy requirements are in part much lower compared with QFPs and TSOPS of the same pitch. The growth rate of the QFP and SO packages is still undiminished. The annual growth rate of BGAs until the turn of the century is by far the highest growth rate of all IC packages. Currently pBGAs and CSP (Chip Size/Scale Packages) with a minimum ball pitch of 0.5 mm are attracting more and more interest. At present at least 20 different companies worldwide are working on that package form family. pBGAs and CSPS, which currently are not yet fully competitive in terms of reliability and price will, outside of Japan, find first larger applications during 1997. Sony already uses lots of CSPS in their newest camcorder model as a substitute of TAB components,.