Flip Chip Assembly Process Optimizations and Material Selections Through Validated Simulations
Authors: Ron Zhang, Rajesh Katkar, Michael Huynh, and Laura Mirkarimi Company: Invensas Corporation Date Published: 4/18/2012
Abstract: To successfully attach semiconductor devices by soldering (die to substrate or package to board), warpage prior to and after the attach process must be carefully monitored and controlled. This paper investigates the effects of material selections and assembly process parameters on warpage at every assembly step by using a step by step FEA simulation approach. A 125 micro m fine pitch Invensas micro PILR™ flip chip package is chosen to demonstrate how simulation techniques in combination with actual warpage measurements can be implemented to provide valuable guidance in fine tuning assembly process parameters and choosing appropriate material sets to ensure package survivability.
Flip Chip, micro PILR, Material Selections, Warpage Simulation, FEA