0.3mm Pitch Chip Scale Package (CSP) Process Development and Printed Circuit Board (PCB) DesignAuthors: Jonas Sjoberg, Ranilo Aranda, and David Geiger
Company: Flextronics Advanced Engineering Group
Date Published: 4/18/2012 Conference: Symposium
This means that the size and pitch of solder balls or pads in the electronic component packages will continue to shrink and that component stacking with so called Package on Package (PoP) will be heavily used.
The use of fine pitch components, equal and below 0.4mm pitch, poses a number of challenges for PCB Design, SMT Assembly process and Reliability.
First, a feasible assembly process must be achieved. The assembly process ranges all the way from screen-printing too in many cases underfill of CSP's, PoP's and LGA's. Many factors influence the quality of the assembly process and with the reduced pitch the process capabilities for both assembly and PCB fabrication will be tested to its limit and beyond.
The basic processes to control are screen-printing, pick&place, reflow soldering with or without the aid of Nitrogen and underfill.
Second, the right materials (such as PCB material, PCB surface finish, solder paste and underfill) and PCB design need to be selected to ensure a high yielding, cost effective and reliable interconnect. Of course the mechanics of the products makes a big difference as well but it is very product dependant and many of today's products leave little room for designing the mechanics in the most reliable way due to total cost and overall looks of the product.
This paper will discuss different design & layout alternatives and assembly & material selection alternatives for 0.3-0.4mm pitch CSP's.
Miniaturization and 0.3mm pitch CSP
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