IWLPC (Wafer-Level Packaging) Conference Proceedings

A Study of a Development Lithography Processes for 3Di Plating Applications

Authors: Patrick Kearney, Kirsten Ruck, Kathleen Nafus, Tetsushi Miyamoto, Patrick Jaenen, and Andrew Miller
Company: Tokyo Electron Europe Limited, Tokyo Electron Kyushu Limited, Inter-University Micro-Electronics Centre
Date Published: 11/5/2012   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The emergence of FBEOL (Far Back End of Line) processes such as MEMS and 3Di has shifted the importance of processing thick films to the forefront in semiconductor production. Finding more efficient processes that satisfy the industry's stringent requirements for low chemical consumptions, fast processing times, and CDU is an ongoing task. FBEOL processes often have large topographies, (10 to 100µm deep) that are difficult to develop and often have substrates that are prone to undercut or peeling. Long process times and high chemical consumption need to be addressed. For both environmental and economic reasons it is important to strive to attain the most efficient systems available.

This paper aims to show a comprehensive developing study into 60µm photoresist films applied to a 3D plating process on 300mm wafers. The end result being the determination of control knobs that facilitate a more efficient and controlled.

Key Words: 

3Di, Films for Plating. Developing thick photoresist films

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