Verification of Back-To-Front Side Alignment for Advanced PackagingAuthors: Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, John Slabbekoorn, and Andy Miller
Company: Ultratech, Inc. and IMEC
Date Published: 11/5/2012 Conference: IWLPC (Wafer-Level Packaging)
Lithography is one of the critical process steps that affect the final device performance and associated yield for TSV manufacturing. One of the unique lithography requirements is the need for back-to-front side alignment. Obtaining precise metrology for measuring back-to-front side overlay performance is an industry challenge. Unlike front end manufacturing where automated metrology tools are widespread, metrology options are limited for back-to-front side overlay. This paper will discuss a metrology package which has been developed to evaluate and qualify back-to-front overlay performance using the lithography tool itself. The package is unique in its capability to measure any location of the wafer and model the acquired data to provide detailed insight in back-to-front side overlay performance.
Silicon test wafers were fabricated over a range of thicknesses to evaluate the stepper self-metrology for back-to-front side overlay. The reference layer is defined in a standard damascene copper process and protected with a passivation layer. Next the wafers are flipped, bonded, and thinned to various thicknesses. Wafers were produced with coarse and fine grinds to compare with chemical mechanical polish (CMP) to assess the impact of surface interference on the alignment system of the lithography tool. Experimental back-to-front alignment metrology data is shown as a function of silicon thickness and surface finish using the lithography tool self-metrology. The accuracy of the tool self-metrology is verified independently using external infrared (IR) microscopy.
Metrology, Overlay, 3D Packaging, TSV, back-to-front side alignment
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