IWLPC (Wafer-Level Packaging) Conference Proceedings


Characterization of eWLB PoP Structures

Author: Tom Strothmann
Company: STATS ChipPAC, Inc
Date Published: 11/5/2012   Conference: IWLPC (Wafer-Level Packaging)


Abstract: eWLB fan-out package technology provides a flexible package platform for 3D package options. Vias placed into the fan-out area provide a convenient method to enable an electrical connection to a top package without the use of TSV’s. This basic capability enables existing silicon designs to be incorporated into high performance PoP structures with a minimal package height. Since there is no laminate used in the bottom package, a total stacked package height of <1.0mm can be achieved. This supports the increasing demand for ever thinner mobile products. The small package size is also advantageous for improved performance. The very short interconnect routing length with thick plated Cu provides superior electrical performance and flexibility in the design. Recent work with traditional stripline features has enabled a 4 layer laminate FC design to be converted to a 2 layer design with eWLB. Critical design considerations for matched pair routing can be relaxed as the line lengths are decreased. Fine pitch lines and spaces used in the package can also reduce the number of interconnect layers required on the board, thereby reducing board cost. Two methods are examined to achieve these advanced PoP structures. The first method uses low density vias that are laser drilled from the topside of the package, enabling a top package connection using 0.4mm pitch and above. The second method uses pre-formed high density vias placed into the fan-out area, enabling a topside redistribution layer. The key attributes of form factor, reliability, warpage, electrical performance, and relative cost will be reviewed for both package types and compared with conventional laminate PoP packages.

Key Words: 

eWLB, PoP, fan-out



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